Radiation hardened by design.
SiGe VCO chip consists of the two VCO cores (PMOS and BJT), digital control block, voltage reference and low-dropout voltage regulators.
VCO tuneable frequency range is 0.83 GHz - 3.48 GHz.
PMOS VCO SSB Phase Noise @ 3.1 GHz: -50.3 dBc/Hz (1 kHz offset), -83.5 dBc/Hz (10 kHz offset), -112.5 dBc/Hz (100 kHz offset), -135.5 dBc/Hz (1 MHz offset), -150.8 dBc/Hz (10 MHz offset),
Three tuning parameters: Analog tuning: 1-8MHz/V, Coarse digital: 3-15MHz/V and Fine digital: 0.1-8MHz/V.
Analog tuning voltage is between 0-2.5V.
VCO is controlled via 4-wire serial peripheral interface (SPI).
Operational temperature range: -40°C…+85°C
Supply Voltage 3.3 (PMOS) and 5.5V (BJT).
Silicon Area (for IP) is 1300 x 2500 mm2.
The Fig 1 shows general architecture and layout of the VCO chip. VCOPMOS is situated on the top while the VCOBJT is placed on the bottom. For short and straightforward wiring, Digital control is placed in the middle. The output buffers are placed as close as possible to RF output pins. The die size without scribe line is approximately 3.0 mm x 3.1 mm.
Figure 1: VCO chip general architecture and layout.
Fig 2 displays picture of the fabricated chip and Fig 3 shows the evaluation board.
Figure 2: Fabricated chip, package opened. ©Sami Sipilä, CoreHW
Figure 3: SiGe VCO evaluation board. ©Sami Sipilä, CoreHW