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The project was based on four major pillars that support the complete structure:
With these concepts in mind, the main objective of the project has been to develop a laboratory model of an on board processor chain that could be used to validate the new algorithms. This laboratory model will be the baseline for new OBP generations, and will allow the procurement of qualified and flight models to potential satellite operators.
The first main objective of the project was to design an end-to-end satellite system that would take into account not only the specificities of the different actors involved but also the operator’s point of view. Afterwards, the impact on the on board processor and on the different sections was analysed and every section of the OBP was detailed.
The final objective was to implement and test in a laboratory model, the newly designed algorithms and to check their performances in a simulated environment.
Thales Alenia Space – España was the prime contractor of the first communications system based on a multispot on board processor fully compliant with the European standards (AmerHis).
The new development sets the basis for the next generation of processors, that include the new standards and techniques (such as DVB-S2 in ACM mode) and enhances the switching capabilities of the satellite to profit from the adaptability in the downlink.
The design of the complete system with the participation of a global satellite operator is crucial to understand the user’s needs and to focus on the key services that make the commercial deployment much easier. Also, the implementation with flight requirements of the different algorithms allows the consortium to reduce the development phase for future on board processors based on these techniques.
It can be said that the activities have bee based on two different architectures. The first one is a high level architecture, that included all the elements in the satellite communications system. It was designed from the end-to-end applications point of view and took into account all the actors and roles that shall be present in the network.
Hybrid system architecture
The second architecture has been developed around the laboratory demonstrator and the implementable units. It is centred in the On Board Processor and it is aimed at validating the new algorithms that were to be implemented. The main building blocks of this demonstrator are the ones composing the OBP (DVB-RCS receiver, switch and DVB-S2 transmitter) that are accompanied by the needed units to prove their good performances (DVB-RCS ground modulator, Random Information Generator, Forward and Return Link Schedulers, Control Unit, etc.). In this laboratory model, the main objective was to implement and validate the physical layer functionalities. Higher lever performances were included in the mandatory cases, such as uplink SYNC packets (DVB-RCS) encapsulation into MPEG or ATM, to be compliant with the downlink standard.
The laboratory demonstrator was built based on three different types of boards mounting BGAs. The only commercial board mounted a Virtex4 BGA. The other two boards have been designed by Thales Alenia Space – España and include several interfaces such as Ethernet link, analog to digital and digital to analog converters, digital inputs / outputs for boards interconnection, several clock inputs, etc.
The project was structured into two phases to be developed over 30 months:
The final review of the project has been successfully held. During the meeting, the different units were reviewed providing a brief description of the new algorithms implemented and a detailed overview of the tests that have been performed on them. The final integration in the laboratory and the adaptability of the forward channel to the link conditions has also been demonstrated.